FPGA Based SCA Resistant AES S-Box Design
نویسندگان
چکیده
A new implementation scheme of AES (Advanced Encryption Standard) is proposed in this paper. The LUT based design of S-box consumes almost 75% of power. Instead of using LUT based S-box, composite field S-box design is used. That can reduce the amount of power consumption. The values of s-box are known to everyone. By masking the each value in the s-box by another masking function increase the system security and reduce the side channel attacks. This masking module can be implemented on any part of AES algorithm and re-masking module is used to remove the mask. It can be used as mask for the entire encrypted message. By using the new implementation of composite field s -box we can save the memory area up to 2.6 Mega Byte that optimizes the chip area and composite field S-box reduces the power consumption and masking module used to increase the system security.
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